////Serial Architecture..... module serial(a,b,clk,s); input [17:0] a; output [17:0] b; input clk,s; wire [17:0] t1,t2,a1; wire co; parameter cin = 1'b0; reg18 m1(a1,clk,1'b0,a); adder_18 m2(a1,t2,cin,t1,co); reg18 m3(t2,clk,s,t1); rsh3 m4(t1,b); endmodule ////Parallel architecture module parallel(a1,a2,a3,a4,a5,a6,a7,a8,clk,b); output [17:0] b; input clk; input [17:0] a1,a2,a3,a4,a5,a6,a7,a8; wire [17:0] t1,t2,t3,t4,t5,t6,t7,t8, t9,t10,t11,t12,t13,t14,t15,t16; wire c1,c2,c3,c4,c5,c6,c7; parameter cin = 1'b0; ////input stage registers..... reg18 m1(t1,clk,reset,a1); reg18 m2(t2,clk,reset,a2); reg18 m3(t3,clk,reset,a3); reg18 m4(t4,clk,reset,a4); reg18 m5(t5,clk,reset,a5); reg18 m6(t6,clk,reset,a6); reg18 m7(t7,clk,reset,a7); reg18 m8(t8,clk,reset,a8); ////adder tree adder_18 m9(t2,t1,cin,t9,c1); adder_18 m10(t4,t3,cin,t10,c2); adder_18 m11(t6,t5,cin,t11,c3); adder_18 m12(t8,t7,cin,t12,c4); adder_18 m13(t10,t9,cin,t13,c5); adder_18 m14(t12,t11,cin,t14,c6); adder_18 m15(t14,t13,cin,t15,c7); ////output stage registers..... reg18 m16(t16,clk,reset,t15); ////wired division by 8 rsh3 m17(t16,b); endmodule ////////Pipelining........ module mean_pipe(a1,a2,a3,a4,a5,a6,a7,a8,clk,b); output [17:0] b; input clk; input [17:0] a1,a2,a3,a4,a5,a6,a7,a8; wire [17:0] t1,t2,t3,t4,t5,t6,t7,t8, t9,t10,t11,t12,t13,t14,t15,t16,t17, t18,t19,t20,t21,t22; wire c1,c2,c3,c4,c5,c6,c7; parameter cin = 1'b0; ////input stage registers..... reg18 d1(t1,clk,reset,a1); reg18 d2(t2,clk,reset,a2); reg18 d3(t3,clk,reset,a3); reg18 d4(t4,clk,reset,a4); reg18 d5(t5,clk,reset,a5); reg18 d6(t6,clk,reset,a6); reg18 d7(t7,clk,reset,a7); reg18 d8(t8,clk,reset,a8); ////adder tree adder_18 m1(t2,t1,cin,t9,c1); adder_18 m2(t4,t3,cin,t10,c2); adder_18 m3(t6,t5,cin,t11,c3); adder_18 m4(t8,t7,cin,t12,c4); //1st stage pipeline registers. reg18 d9(t13,clk,reset,t9); reg18 d10(t14,clk,reset,t10); reg18 d11(t15,clk,reset,t11); reg18 d12(t16,clk,reset,t12); adder_18 m5(t14,t13,cin,t17,c5); adder_18 m6(t16,t15,cin,t18,c6); //2nd stage pipeline registers. reg18 d13(t19,clk,reset,t17); reg18 d14(t20,clk,reset,t18); adder_18 m7(t19,t20,cin,t21,c7); ////output stage registers..... reg18 d15(t22,clk,reset,t21); ////wired division by 8 rsh3 m8(t22,b); endmodule //////////Sub blocks... module adder_18(a,b,cin,sum,co); input [17:0] a,b; input cin; output [17:0] sum; output co; wire c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15,c16,c17; fa m1(a[0],b[0],cin,sum[0],c1); fa m2(a[1],b[1],c1,sum[1],c2); fa m3(a[2],b[2],c2,sum[2],c3); fa m4(a[3],b[3],c3,sum[3],c4); fa m5(a[4],b[4],c4,sum[4],c5); fa m6(a[5],b[5],c5,sum[5],c6); fa m7(a[6],b[6],c6,sum[6],c7); fa m8(a[7],b[7],c7,sum[7],c8); fa m9(a[8],b[8],c8,sum[8],c9); fa m10(a[9],b[9],c9,sum[9],c10); fa m11(a[10],b[10],c10,sum[10],c11); fa m12(a[11],b[11],c11,sum[11],c12); fa m13(a[12],b[12],c12,sum[12],c13); fa m14(a[13],b[13],c13,sum[13],c14); fa m15(a[14],b[14],c14,sum[14],c15); fa m16(a[15],b[15],c15,sum[15],c16); fa m17(a[16],b[16],c16,sum[16],c17); fa m18(a[17],b[17],c17,sum[17],c0); endmodule module reg18(y,clk,reset,a); input [17:0] a; output [17:0] y; input clk,reset; DFF d1(y[0],clk,reset,a[0]); DFF d2(y[1],clk,reset,a[1]); DFF d3(y[2],clk,reset,a[2]); DFF d4(y[3],clk,reset,a[3]); DFF d5(y[4],clk,reset,a[4]); DFF d6(y[5],clk,reset,a[5]); DFF d7(y[6],clk,reset,a[6]); DFF d8(y[7],clk,reset,a[7]); DFF d9(y[8],clk,reset,a[8]); DFF d10(y[9],clk,reset,a[9]); DFF d11(y[10],clk,reset,a[10]); DFF d12(y[11],clk,reset,a[11]); DFF d13(y[12],clk,reset,a[12]); DFF d14(y[13],clk,reset,a[13]); DFF d15(y[14],clk,reset,a[14]); DFF d16(y[15],clk,reset,a[15]); DFF d17(y[16],clk,reset,a[16]); DFF d18(y[17],clk,reset,a[17]); endmodule module rsh3(a,b); input [17:0] a; output [17:0] b; assign {b[17:14],b[13:0]}= {a[17],a[17],a[17],a[17],a [16:3]}; endmodule