Static Timing Analysis using Cadence Tempus

In the previous tutorials, we have discussed how to simulate or synthesize a design using Synopsys or Cadence. Static Timing Analysis is a very important step in designing an digital design for ASIC. This tutorial is on performing Static Timing Analysis using Cadence Tempus. 1. Open the terminal 2.   Source the cadence.cshrc 3.   In this […]