Tag Archives: State Minimization Techniques for FSM

Row Equivalence Method for State Minimization

Row Equivalence Method for State Minimization is a very simple technique to reduce number of states of an FSM. In the row equivalence method, it is checked that rows of a state table are equivalent or not. Here, a comparatively strict definition of state equivalence is used. The conditions for two states and to be… Read More »

State Minimization Techniques for FSM

In the previous post FSM Design, we have discussed design of Mealy and Moore state machines using Verilog. State minimization is important if we want to reduce number of states in a complex FSM which has many redundant states. If the number of states are reduced then number of bits required for state assignment will… Read More »