Which of the following is a valid Verilog data type?
In Verilog, the keyword reg is used to declare:
What is the default value of an uninitialized reg in Verilog simulation?
Which of the following statements about blocking (=) and non-blocking (
Which of the following is NOT a valid Verilog simulation time unit?
In Verilog, what is the function of the timescale directive?
Which statement is TRUE about wire in Verilog?
What is the period of the clock signal? always #5 clk = ~clk;
In Verilog, $finish is used to:
Which operator has the highest precedence in Verilog?
Which of the following is TRUE about Verilog simulation phases?
In Verilog, the keyword parameter is used for:
What is the output? reg [3:0] a; initial begin a = 4'b1001; a = ~a; $display("%b", a); end
Which of the following can only be used in simulation (not synthesis)?
In Verilog, casez differs from casex because:
What is the output? reg [3:0] x; initial begin x = 4'b1011; x = (x > 2); x = ~x; x = x + 4'b0101; end
Which signal type is preferred for combinational logic outputs in Verilog?
In synthesis, what will happen if an always block with posedge clk has no reset and no assignment in some cases?
Which statement is TRUE about generate blocks?
What will be displayed? integer i; initial begin for (i = 0; i < 3; i = i + 1) $display(i); end
Which is NOT a valid port connection style?
If a signal is declared as tri in Verilog, it means:
Which will infer a latch in synthesis? always @(*) begin if (en) y = d; end
Which operator in Verilog is used for logical equality comparison?
What is output? reg [3:0] a = 4'd5; initial begin $display("%d", a / 2); end
Which of the following keywords is NOT in standard Verilog-2001?
Which is TRUE about $monitor?
What is output? reg [3:0] a = 4'b1010; initial begin $display("%b", {a[1:0], a[3:2]}); end
Which of these delay statements is correct in Verilog?
In synthesis, $display statements are:
