Power Analysis using Synopsys

In the previous tutorials, simulation and synthesis of digital circuits are described. This tutorial is on Power Analysis using Synopsys. Here, dynamic power consumption of a sequential circuit is estimated. 1.   Open the terminal 2.   Source the synopsys.cshrc 3.   In this experiment, we perform power analysis (dynamic power) of the design using power compiler. 4.  […]

ATPG for Sequential circuits

Automatic Test Pattern Generation and Automatic Test Pattern Generator (ATPG) is an electronic design automation method/technology used to find an input (or test) sequence that, when applied to a digital circuit, enables automatic test equipment to distinguish between the correct circuit behavior and the faulty circuit behavior caused by defects. Earlier we presented a tutorial on ATPG for Combinational Circuits. This tutorial focuses on ATPG for sequential circuits […]

ATPG for Combinational Circuits

Automatic Test Pattern Generation and Automatic Test Pattern Generator (ATPGA) is an electronic design automation method/technology used to find an input (or test) sequence that, when applied to a digital circuit, enables automatic test equipment to distinguish between the correct circuit behavior and the faulty circuit behavior caused by defects. This tutorial focuses on ATPG for combinational circuits using Synopsys Tetramax tool. 1.   Open the terminal 2.   Source […]

Synopsys Simulation and Synthesis

Here, tutorial on simulation of Verilog file using Synopsys EDA tool is given. Also, synthesis using Deign Vision tool is also shown. The reader find this tutorial on Synopsys Simulation and Synthesis very useful. 1.   Open the terminal 2.   Source the synopsys.cshrc 3.   Check whether the commands are working as below. Terminal will echo the […]

ASIC Tutorials I

Here, we will discuss the tutorials on how to synthesize a Verilog code starting from simulation, syntax checking, code coverage using CADENCE EDA tool. Basic Simulation on CADENCE Linting Code Coverage Logic Equivalence Check Genus Synthesis without Constraints Genus Synthesis with Constraints Genus Synthesis using Scripts Static Timing Analysis using Cadence Tempus 00

GENUS Synthesis using SCRIPTS

In our earlier tutorials [GENUS Synthesis With Constraints, GENUS Synthesis Without Constraints] on synthesis of Verilog files using Cadence Genus tool, we have seen how synthesis can be performed with or without timing constraints. But it is very painful to perform synthesis operation by executing commands one by one in the command prompt. Thus industry […]

GENUS Synthesis With Constraints

This tutorial is in continuation with our previous tutorial on Genus Synthesis Without Constraints (Timing Constraints). The timing constraints are written in Synopsys Design Constraint (SDC) file. 1. Open the terminal and type csh 2. Source the cadence.cshrc. 3. In ASIC lab folder, make a new directory. In this, make design.v (in this example counter.v). […]

GENUS Synthesis Without Constraints

In this tutorial Cadence GENUS Synthesis without Constraints is presented. 1. Open the terminal and type csh 2. Source the cadence.cshrc. After sourcing the file, check whether genus is installed in the current system or not by typing the below command [sudi@sankh]$ which genus 3.  In ASIC lab folder, make a new directory. Make design.v […]

Logic Equivalence Checking

Logic Equivalence Checking is a very important step to be performed after synthesis step. This operation checks for similarity between the original code and the synthesis Netlist. This operation is important as the synthesis tool may trim or remove some unused and unconnected ports and redundant logics. The steps of performing Logic Equivalence Checking in […]