module ANN_XOR (input [11:0] x1,x2, output y);

wire [11:0] t1,t2;
wire equal1,greater1,equal2,greater2,a1,a2,b1,b2;

parameter th = 12'b00_1000000000;
/////Input node 1
adsubN #(12) ad1(x1[11],'d0,x1,t1);
comparatorNbit #(12) comp1(t1,th,,equal1,greater1);
assign b1 = equal1 | greater1 ;
 

/////Input node 2
adsubN #(12) ad2(x2[11],'d0,x2,t2);
comparatorNbit #(12) comp2(t2,th,,equal2,greater2);
assign b2 = equal2 | greater2 ;

////Hidden nodes...
assign a1 = b1 | b2;
assign a2 = ~(b1 & b2);

////Output node
assign y = a1 & a2;
endmodule

module adsubN #(parameter N = 18)(input sel,input [N-1:0] a,b,
output [N-1:0] s
    );
assign s = (sel)?(a-b):(a+b);

endmodule

module comparatorNbit #(parameter N=18)(a,b,less,equal,greater);
input  [N-1:0] a;
input  [N-1:0] b;
output reg less;
output reg equal;
output reg greater;
always@(a or b)
begin
if(a>b) begin
  less=0;
  equal=0;
  greater=1;
end
else if(a==b) begin
  less=0;
  equal=1;
  greater=0;
end
else begin
  less=1;
  equal=0;
  greater=0;
  end
end
endmodule



`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 20.11.2023 15:16:39
// Design Name: 
// Module Name: ANN_XOR_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module ANN_XOR_tb();
reg [11:0] x1,x2;
wire y;

ANN_XOR uut(x1,x2,y);

initial begin
x1 = 12'b001000000000;//0.5
x2 = 12'b001100000000;//0.75
#100;
x1 = 12'b000100000000;//0.25
x2 = 12'b001100000000;//0.75
#100;
x1 = 12'b000100000000;//0.25
x2 = 12'b000100000000;//0.25
#100;
x1 = 12'b001110000000;//0.875
x2 = 12'b000100000000;//0.75
#100;
x1 = 12'b111000000000;//-0.5
x2 = 12'b001100000000;//0.75
end
endmodule