`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    09:53:39 07/25/2020 
// Design Name: 
// Module Name:    mult_table 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module mult_table(a,b,p
    );
input [3:0] a,b;
output [5:0] p;
wire [3:0] p1,p2;
wire [5:0] p3,p4,p5;

adsub4 ad1(1'b0,a,b,p1);
adsub4 ad2(1'b1,a,b,p2);
squaringtable m1(p1,p3);
squaringtable m2(p2,p4);
adsub8 ad3(1'b1,p3,p4,p);
endmodule

module adsub4 (sel,c,a,p);
  input sel;
  input [3:0] a,c;
  output [3:0] p;
 assign p = (sel)?(c-a):(c+a);
endmodule

module adsub8 (sel,c,a,p);
  input sel;
  input [5:0] a,c;
  output [5:0] p;
 assign p = (sel)?(c-a):(c+a);
endmodule

module squaringtable(addres,data_out);
input [3:0] addres;
output reg [5:0] data_out;
//reg [3:0] mem [0:7];
initial begin data_out = 6'b000000; end
always @ (addres)
case (addres)
4'b0000 : data_out = 6'b000000;
4'b0001 : data_out = 6'b000000;
4'b0010 : data_out = 6'b000001;
4'b0011 : data_out = 6'b000010;
4'b0100 : data_out = 6'b000100;
4'b0101 : data_out = 6'b000110;
4'b0110 : data_out = 6'b001001;
4'b0111 : data_out = 6'b001100;
4'b1000 : data_out = 6'b010000;
4'b1001 : data_out = 6'b010100;
4'b1010 : data_out = 6'b011001;
4'b1011 : data_out = 6'b011110;
4'b1100 : data_out = 6'b100100;
4'b1101 : data_out = 6'b101010;
4'b1110 : data_out = 6'b110001;
4'b1111 : data_out = 6'b111000;
endcase
endmodule