### Scheme 1 module clk_div_1p5(clk,reset,clk_1p5); input clk,reset; output clk_1p5; wire clk1,clk_dv3; mux m1(~clk,clk,clk_dv3,clk1); clk_div_3 m2(clk_dv3,clk,reset); tff m3(clk_1p5,reset,clk1,1'b1); endmodule module tff(q,reset,clk,t); output reg q; input t,reset,clk; initial begin q=1'b0; end always @ (posedge clk) if (reset) q <= 1'b0; else if (t) q= ~q; else q = q; endmodule module clk_div_3(clk_out,clk,reset); input clk,reset; output clk_out; wire t1,clkb,q0,q1,q2; assign clkb = ~clk; assign t1 = ~q0 & ~q1; dff m1(q0,reset,clk,t1); dff m2(q1,reset,clk,q0); dff m3(q2,reset,clkb,q1); assign clk_out = q2 | q1; endmodule module dff(q,reset,clk,d); output reg q; input reset,d,clk; initial begin q=1'b0; end always @ (posedge clk) if (reset) q <= 1'b0; else q<=d; endmodule module mux(A,B,S,Y); input A,B; output Y; input S; assign Y = (S)? B : A; endmodule ////////////////////////////////////////////////////////// ### Scheme 3 module clk_div_1p5_2(clk,reset,clk_out ); input clk,reset; output clk_out; wire t1,t2,t3,q0,q1; clk_dv3_2 m1(q0,q1,clk,reset); //assign t1 = q1 & ~clk; \\alternative according to [1]. //assign t2 = clk & t3; \\alternative //assign t3 = t1 | t2; \\alternative assign t3 = q1 ^ clk; assign clk_out = t3 | q0; endmodule module clk_dv3_2(q0,q1,clk,reset); input clk,reset; output q0,q1; wire t; dff m2(q0,reset,clk,t); dff m3(q1,reset,clk,q0); assign t = (~q0) & (~q1); endmodule ////////////////////////////////////////////////////////// #####Scheme 2 module clk_div_4p5(clk,reset,clk_4p5 ); input clk,reset; output clk_4p5; wire d1,d2,d3,d4,d5,d6,d7,d8,d9,d51,d61,t1,t2; dff m1(d1,reset,clk,d9); dff m2(d2,reset,clk,d1); dff m3(d3,reset,clk,d2); dff m4(d4,reset,clk,d3); dff m5(d5,reset,clk,d4); dff m6(d6,reset,clk,d5); dff m7(d7,reset,clk,d6); dff m8(d8,reset,clk,d7); dff1 m9(d9,reset,clk,d8); dff m10(d51,reset,~clk,d5); dff m11(d61,reset,~clk,d6); assign t1 = d51 | d61; assign t2 = d1 | d2; assign clk_4p5 = t1 | t2; endmodule module dff1(q,reset,clk,d); output reg q; input reset,d,clk; initial begin q=1'b0; end always @ (posedge clk) if (reset) q <= 1'b1; else q<=d; endmodule ///////////////////////////////////////////////////////////////// module clk_dv_2p5(clk,reset,clk_out ); input clk,reset; output clk_out; wire t1,t2,q0,q1,q2; clk_dv5_2 m1(q0,q1,q2,clk,reset); //assign t1 = q1 & q2 & ~clk; \\alternative as per [1] //assign t2 = clk & t3; \\alternative //assign t3 = t1 | t2; \\alternative assign t3 = (~clk & q1 & q2) | (clk & ~q1 & q2); assign clk_out = t3 | q0; endmodule module clk_dv5_2(q0,q1,q2,clk,reset ); input clk,reset; output q0,q1,q2; wire t1,t2,t3; dff m1(q0,reset,clk,t1); dff m2(q1,reset,clk,t3); dff m3(q2,reset,clk,q1); assign t1 = (~q0) & (~q1) & (~q2); assign t2 = q0 | q1; assign t3 = t2 & (~q2); endmodule /////////////////////////////////////////////////////////////////