`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    21:59:55 05/21/2020 
// Design Name: 
// Module Name:    sorting3 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module sorting3(clk,reset,start,a1,a2,a3,a4,a5,a6,a7,a8,b1,b2,b3,b4,b5,b6,b7,b8
    );
input [15:0] a1,a2,a3,a4,a5,a6,a7,a8;
output [15:0] b1,b2,b3,b4,b5,b6,b7,b8;
input clk,reset,start;
wire [15:0] t1,t2,t3,t4,t5,t6,t7,t8,t9,t10,t11,t12,t13,t14,t15,t16,t17,t18,t19,t20,t21,t22,t23,t24,t25,t26,
t27,t28,t29,t30,t31,t32,t33,t34,t35,t36,t37,t38,t39,t40,t41,t42;
wire [15:0] c1,c2,c3,c4,c5,c6,c7,c8;
mux16 mx1(b1,a1,start,c1);
mux16 mx2(b2,a2,start,c2);
mux16 mx3(b3,a3,start,c3);
mux16 mx4(b4,a4,start,c4);
mux16 mx5(b5,a5,start,c5);
mux16 mx6(b6,a6,start,c6);
mux16 mx7(b7,a7,start,c7);
mux16 mx8(b8,a8,start,c8);


BN1 m1(c1,c2,t1,t2);
BN1 m2(c3,c4,t3,t4);
BN1 m3(c5,c6,t5,t6);
BN1 m4(c7,c8,t7,t8);

BN1 m5(t2,t3,t9,t10);
BN1 m6(t4,t5,t11,t12);
BN1 m7(t6,t7,t13,t14);

reg16 rg1(b1,clk,reset,t1);
reg16 rg2(b2,clk,reset,t9);
reg16 rg3(b3,clk,reset,t10);
reg16 rg4(b4,clk,reset,t11);
reg16 rg5(b5,clk,reset,t12);
reg16 rg6(b6,clk,reset,t13);
reg16 rg7(b7,clk,reset,t14);
reg16 rg8(b8,clk,reset,t8);

endmodule

module mux16(A,B,S,Y);

    input [15:0] A,B;
    output [15:0] Y;
    input S;

assign Y = (S)? B : A;
endmodule

module BN1(A,B,max,min
    );
input [15:0] A,B;
output [15:0] max,min;
wire LT1,GT1,EQ1;
comp16 m1(A,B,LT1,GT1,EQ1);
mux16 mx1(A,B,LT1,max);
mux16 mx2(B,A,LT1,min);
endmodule

module comp16(A1,B1,LT1,GT1,EQ1);
    input [15:0] A1,B1;
   
    output reg LT1,GT1,EQ1;
	 always @ (A1,B1)
	 begin
	 if (A1>B1)
	 begin
	 LT1 <= 0; GT1 <= 1; EQ1 <= 0;
	 end
	 else if (A1<B1)
	 begin
	 LT1 <= 1; GT1 <= 0; EQ1 <= 0;
	 end
	 else
	 begin
	 LT1 <= 0; GT1 <= 0; EQ1 <= 1;
	 end
	 end
endmodule


module reg16(y,clk,reset,a);
    input [15:0] a;
    output [15:0] y;
    input clk,reset;
 
DFF d1(y[0],clk,reset,a[0]);
DFF d2(y[1],clk,reset,a[1]);
DFF d3(y[2],clk,reset,a[2]);
DFF d4(y[3],clk,reset,a[3]);
DFF d5(y[4],clk,reset,a[4]);
DFF d6(y[5],clk,reset,a[5]);
DFF d7(y[6],clk,reset,a[6]);
DFF d8(y[7],clk,reset,a[7]);
DFF d9(y[8],clk,reset,a[8]);
DFF d10(y[9],clk,reset,a[9]);
DFF d11(y[10],clk,reset,a[10]);
DFF d12(y[11],clk,reset,a[11]);
DFF d13(y[12],clk,reset,a[12]);
DFF d14(y[13],clk,reset,a[13]);
DFF d15(y[14],clk,reset,a[14]);
DFF d16(y[15],clk,reset,a[15]);

endmodule

module DFF(q,clk,reset,d);
    input d,clk,reset;
    output reg q;
initial begin q=0; end
always @ (posedge (clk)) begin
 if (reset)
  q <= 0;
 else  
 q<= d ;
end
endmodule