`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    10:01:45 05/22/2020 
// Design Name: 
// Module Name:    bubblesot 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module bubblesot(clk,reset,start,a1,a2,a3,a4,a5,a6,a7,a8,b1,b2,b3,b4,b5,b6,b7,b8
    );
input [15:0] a1,a2,a3,a4,a5,a6,a7,a8;
output [15:0] b1,b2,b3,b4,b5,b6,b7,b8;
input clk,reset,start;
wire [15:0] t1,t2,t3,t4,t5,t6,t7,t8,t9,t10,t11,t12,t13,t14;
wire [15:0] c1,c2,c3,c4,c5,c6,c7,c8;

mux16 mx1(b1,a1,start,c1);
mux16 mx2(b2,a2,start,c2);
mux16 mx3(b3,a3,start,c3);
mux16 mx4(b4,a4,start,c4);
mux16 mx5(b5,a5,start,c5);
mux16 mx6(b6,a6,start,c6);
mux16 mx7(b7,a7,start,c7);
mux16 mx8(b8,a8,start,c8);

BN1 m1(c1,c2,t1,t2);
BN1 m2(t2,c3,t3,t4);
BN1 m3(t4,c4,t5,t6);
BN1 m4(t6,c5,t7,t8);
BN1 m5(t8,c6,t9,t10);
BN1 m6(t10,c7,t11,t12);
BN1 m7(t12,c8,t13,t14);

reg16 rg1(b1,clk,reset,t1);
reg16 rg2(b2,clk,reset,t3);
reg16 rg3(b3,clk,reset,t5);
reg16 rg4(b4,clk,reset,t7);
reg16 rg5(b5,clk,reset,t9);
reg16 rg6(b6,clk,reset,t11);
reg16 rg7(b7,clk,reset,t13);
reg16 rg8(b8,clk,reset,t14);
endmodule