`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    19:48:39 05/21/2020 
// Design Name: 
// Module Name:    sorting1 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module sorting1(a1,a2,a3,a4,a5,a6,a7,a8,t9,t17,t23,t24,t25,t26,t22,t16
    );
input [15:0] a1,a2,a3,a4,a5,a6,a7,a8;
output [15:0] t9,t17,t23,t24,t25,t26,t22,t16;
wire [15:0] t1,t2,t3,t4,t5,t6,t7,t8,t9,t10,t11,t12,t13,t14,t15,t16,t17,t18,t19,t20,t21,t22,t23,t24,t25,t26;
sort4 m1(a1,a2,a3,a4,t1,t2,t3,t4);
sort4 m2(a5,a6,a7,a8,t5,t6,t7,t8);

BN1 m3(t1,t5,t9,t10);
BN1 m4(t2,t6,t11,t12);
BN1 m5(t3,t7,t13,t14);
BN1 m6(t4,t8,t15,t16);

BN1 m7(t10,t11,t17,t18);
BN1 m8(t12,t13,t19,t20);
BN1 m9(t14,t15,t21,t22);

BN1 m10(t18,t19,t23,t24);
BN1 m11(t20,t21,t25,t26);
endmodule

module sort4(a1,a2,a3,a4,mx3,mx5,mn5,mn4
    );
input [15:0] a1,a2,a3,a4;
output [15:0] mx3,mx5,mn5,mn4;
wire [15:0] mx1,mx2,mx3,mx4;
wire [15:0] mn1,mn2,mn3,mn4;

BN1 m1(a1,a2,mx1,mn1);
BN1 m2(a3,a4,mx2,mn2);

BN1 m3(mx1,mx2,mx3,mn3);
BN1 m4(mn1,mn2,mx4,mn4);

BN1 m5(mn3,mx4,mx5,mn5);

endmodule

module BN1(A,B,max,min
    );
input [15:0] A,B;
output [15:0] max,min;
wire LT1,GT1,EQ1;
comp16 m1(A,B,LT1,GT1,EQ1);
mux16 mx1(A,B,LT1,max);
mux16 mx2(B,A,LT1,min);
endmodule

module mux16(A,B,S,Y);

    input [15:0] A,B;
    output [15:0] Y;
    input S;

assign Y = (S)? B : A;
endmodule

module comp16(A1,B1,LT1,GT1,EQ1);
    input [15:0] A1,B1;
   
    output reg LT1,GT1,EQ1;
	 always @ (A1,B1)
	 begin
	 if (A1>B1)
	 begin
	 LT1 <= 0; GT1 <= 1; EQ1 <= 0;
	 end
	 else if (A1<B1)
	 begin
	 LT1 <= 1; GT1 <= 0; EQ1 <= 0;
	 end
	 else
	 begin
	 LT1 <= 0; GT1 <= 0; EQ1 <= 1;
	 end
	 end
endmodule