`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 20:47:22 05/21/2020 // Design Name: // Module Name: sorting2 // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module sorting2(a1,a2,a3,a4,a5,a6,a7,a8,b1,b2,b3,b4,b5,b6,b7,b8 ); input [15:0] a1,a2,a3,a4,a5,a6,a7,a8; output [15:0] b1,b2,b3,b4,b5,b6,b7,b8; wire [15:0] t1,t2,t3,t4,t5,t6,t7,t8,t9,t10,t11,t12,t13,t14,t15,t16,t17,t18,t19,t20,t21,t22,t23,t24,t25,t26, t27,t28,t29,t30,t31,t32,t33,t34,t35,t36,t37,t38,t39,t40,t41,t42; BN1 m1(a1,a2,t1,t2); BN1 m2(a3,a4,t3,t4); BN1 m3(a5,a6,t5,t6); BN1 m4(a7,a8,t7,t8); BN1 m5(t2,t3,t9,t10); BN1 m6(t4,t5,t11,t12); BN1 m7(t6,t7,t13,t14); BN1 m8(t1,t9,t15,t16); BN1 m9(t10,t11,t17,t18); BN1 m10(t12,t13,t19,t20); BN1 m11(t14,t8,t21,t22); BN1 m12(t16,t17,t23,t24); BN1 m13(t18,t19,t25,t26); BN1 m14(t20,t21,t27,t28); BN1 m15(t15,t23,t29,t30); BN1 m16(t24,t25,t31,t32); BN1 m17(t26,t27,t33,t34); BN1 m18(t28,t22,t35,t36); BN1 m19(t30,t31,t37,t38); BN1 m20(t32,t33,t39,t40); BN1 m21(t34,t35,t41,t42); BN1 m22(t29,t37,b1,b2); BN1 m23(t38,t39,b3,b4); BN1 m24(t40,t41,b5,b6); BN1 m25(t42,t36,b7,b8); endmodule module BN1(A,B,max,min ); input [15:0] A,B; output [15:0] max,min; wire LT1,GT1,EQ1; comp16 m1(A,B,LT1,GT1,EQ1); mux16 mx1(A,B,LT1,max); mux16 mx2(B,A,LT1,min); endmodule